Technology#07 in July 2026 EditionMonolithic 3D integration of carbon nanotube field-effect transistors on 300 mm silicon wafers
Kavita Rao, Christopher Jenkins, Bo-Wen Sun et al.
OPENSTEM EDITORIAL SUMMARY
What the research examines
Engineers demonstrate back-end-of-line compatible monolithic 3D fabrication of semiconducting carbon nanotube transistors directly above silicon CMOS logic layers, achieving sub-200 °C thermal budget and 1.8 mA/um on-current density.
Why it may matter
Offers a viable hardware scaling trajectory to extend Moore's law into high-density 3D computing blocks.
What to examine carefully
Residual metallic nanotube impurities in the array lead to leakage current variations that degrade wafer yield.
Editorial scope: This is a concise, independently written introduction based on the publisher information, not a full systematic review or independent replication. It must not replace reading the original methods, limitations and conclusions.
STUDENT RESEARCH LENS · ORIGINAL OPENSTEM NOTES
Try a small, reproducible follow-up
Simulate drain-induced barrier lowering (DIBL) and subthreshold swing in 10-nm gate-length carbon nanotube FETs using drift-diffusion models.
Questions to investigate
- What alignment technique was utilized to achieve aligned nanotube pitch density on 300-mm wafers?
- How was gate dielectric interface trap density minimized under low-temperature deposition?
These are independently proposed educational investigations, not activities that the original research authors claim to have completed.
Publication & researcher information
JournalNature Electronics
Published online2026-07-11
Authors (selected)Kavita Rao, Christopher Jenkins, Bo-Wen Sun et al.
University / laboratoryMassachusetts Institute of Technology
CountryUnited States
Multi-author research may involve universities in several countries. Unverified institutions and contact addresses are not inferred from authors' names.