Technology#08 in June 2026 EditionEnergy-efficient in-memory computing for sparse matrix multiplication using multi-level phase-change memory
Claudio Bellini, Jin-Woo Choi, Martin Gallagher et al.
OPENSTEM EDITORIAL SUMMARY
What the research examines
Engineers fabricate an analog crossbar tile based on antimony-telluride phase-change memory devices capable of 4-bit per cell storage, achieving 62 Tera-operations per second per watt (TOPS/W) on highly sparse deep learning tensor kernels.
Why it may matter
Drastically lowers memory-wall energy consumption for edge AI accelerators and generative language model inference.
What to examine carefully
Structural relaxation (resistance drift) in amorphous phase-change materials requires periodic calibration algorithms.
Editorial scope: This is a concise, independently written introduction based on the publisher information, not a full systematic review or independent replication. It must not replace reading the original methods, limitations and conclusions.
STUDENT RESEARCH LENS · ORIGINAL OPENSTEM NOTES
Try a small, reproducible follow-up
Model conductance drift in phase-change memory devices and simulate neural network inference degradation over a 1-year timeline.
Questions to investigate
- How were zero-valued activations skipped in the analog domain to maximize energy savings?
- What digital-to-analog converter (DAC) resolution was found to balance area cost and precision?
These are independently proposed educational investigations, not activities that the original research authors claim to have completed.
Publication & researcher information
JournalIEEE Transactions on Electron Devices
Published online2026-06-15
Authors (selected)Claudio Bellini, Jin-Woo Choi, Martin Gallagher et al.
University / laboratoryIBM Research Europe - Zurich
CountrySwitzerland
Multi-author research may involve universities in several countries. Unverified institutions and contact addresses are not inferred from authors' names.